Design and analysis of 2x4 decoder using 16 nm technology

Abstract

In this research, we used state-of-the-art 16nm technology to construct and evaluate a 2x4 decoder. The suggested decoder paves the way for flexible digital system applications by effectively translating a 2- bit binary input into one of four distinct output lines. The design solves the fundamental problems with scaling in contemporary semiconductor technology by optimising power consumption, speed, and space using novel approaches. Running thorough simulations and analysing the results allows one to evaluate important
aspects like as latency, power dissipation, and layout efficiency. The results show that the suggested decoder outperforms the
conventional systems, suggesting it might be a good option for digital applications in the future. In addition, the suggested design
is sturdy, and we look at how process variability affects nanoscale device durability. This study's findings add to the growing body of knowledge on designing high-performance digital circuits with minimal power consumption at technology nodes smaller than 20 nm.