Performance Analysis Of Generic Full Adder Based On modified Technique

Abstract

This study explores the similarities and differences of fulladder circuits that use on CMOS technology. The foundation of our
approach is a hybrid design that integrates many fully functional adder circuits. The complete adder circuit is a crucial
component of several designs for digital systems. Data processing units (DSPs), microcontrollers, microprocessors, and digital signal processors are just a few of the many uses for it. The bulk of these systems have their heads situated on the crucial path, which determines the overall speed of the system. When it comes to computing, complete adders are the way to go for VLSI devices like microprocessors. We propose a full adder cell that improves area efficiency while reducing power consumption. Interest in this area of
research has lately skyrocketed due to the growing need for robust and efficient computer systems. Building and comparing the power capacities of entire adder circuits in various technologies is themain objective of this research. We have used the hybrid structure of NMOS and PMOS to create a ladder circuit