COMPARATIVE ANALYSIS 4:1 MULTIPLEXER USING CMOS TECHNOLOGY NANOMETER REGIME

Abstract

Miniaturisation has made power consumption and die area reduction the two most important criteria for each new circuit design. An important digital circuitis the multiplexer. Among the many possible circuit implementations are adders, subtracters, and form SOP
functions. This study analyses several technological nodes using the multiplexer's power and latency metrics. And, OR, and
NAND gates with TG gate types have been created using regular MOSFETs in 32 nm and 45 nm technologies. Here we compared the following performance metrics: average power, power delay product, energy-delay product, delay as a function of process parameters, and supply voltage and temperature. A lower-tech node consumes more power than a higher- tech one, but it takes up more space. But high-speed is the most basic kind of technology.At 32 nm, the supply voltage drops by 33%, the delay increases by 20.94%, and the power drops by 90.82%; at the same wavelength, the delay increases by 193.72% and the power drops by 84.75%.